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Texas Instruments TDEL3G511/-Q1 Triple Rising Edge Delay Elements

Texas Instruments TDEL3G511/-Q1 Triple Rising Edge Delay Elements contain three independent fixed-time delay channels. Each channel on the TDEL3G511/-Q1 is designed to delay the rising edge of an input signal while allowing the falling edge to pass through with minimal delay. This behavior enables the devices to extend short active-low pulses, filter short active-high pulses, and debounce active-low signals.

The TI TDEL3G511/-Q1 Elements use preconfigured digital timing and require no external timing components. Schmitt-trigger inputs improve signal handling, while I/O clamp diodes protect against overvoltage and undervoltage transients. The TDEL3G511-Q1 adds AEC-Q100 qualification for automotive applications.

Features

  • TDEL3G511-Q1 AEC-Q100 qualified for automotive applications
    • Device temperature Grade 1 with -40°C to +125°C ambient operating temperature
    • HBM ESD classification Level 2
    • CDM ESD classification Level C4B
  • Three independent rising-edge delay channels
  • Rising-edge delay with minimal falling-edge delay
  • Preconfigured digital timing without external timing components
  • Schmitt-trigger architecture on all inputs
  • I/O clamp diodes for overvoltage and undervoltage transient protection
  • Push-pull outputs
  • Shared oscillator and control logic across the three channels

Applications

  • Delay the rising edge of a signal
  • Extend a short active-low pulse
  • Filter out short active-high pulses
  • Debounce an active-low signal

Specifications

  • Three delay channels
  • Fixed delay time of approximately 100ms
  • Typical delay variation of 1%
  • Maximum delay variation of 10%
  • Supply voltage range of 1.65V to 5.5V
  • Typical supply current of 3µA
  • Maximum output drive current
    • 12mA low-level output current
    • -12mA high-level output current
  • Maximum continuous digital output current of ±20mA
  • Maximum pulsed digital output current of ±100mA for 1µs
  • Maximum continuous current through VCC or GND of ±60mA
  • Three Schmitt-trigger inputs
  • Three push-pull outputs
  • 8-pin SOT-5X3 package
  • Package dimensions of 2.1mm x 1.6mm

Evaluation Module

Texas Instruments 5-8-LOGIC-EVM评估模块

设计用于支持采用DBV、DCK、DCT、DCU和DRL封装的引脚型逻辑器件。

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Datasheets

Pinout Diagram

Location Circuit - Texas Instruments TDEL3G511/-Q1 Triple Rising Edge Delay Elements

Functional Block Diagram

Block Diagram - Texas Instruments TDEL3G511/-Q1 Triple Rising Edge Delay Elements
发布日期: 2026-09-14 | 更新日期: 2026-09-17