Analog Devices Inc. 亚德诺半导体 ADF7024 低功耗、次 GHz、收发器集成电路

亚德诺半导体 ADF7024 低功耗、次 GHz 收发器集成电路是超低功耗的集成收发器,被设计用于免执照 ISM 频段 433MHz、868MHz 和 915MHz。 ADF7024 简单易用,性能极高,适合各种无线应用。该器件适用于符合欧洲 ETSI EN300-220 法规、北美 FCC Part 15 法规及其他类似法规标准的工作环境。ADF7024 支持多种预先定义的无线配置文件。对于每个无线配置文件,都提供了针对 ADF7024 无线电进行优化的寄存器设置。这确保了 RF 通信层无缝工作,让用户专注于协议和系统级设计及原型制作。无线配置文件涵盖了常用的数据速率和调制选项。

ADF7024 daughter boards are intended for use with the EVAL-ADF7XXXMB4Z mother board. EVAL-ADF7024DB1Z is offered as a 4-layer 862-928MHz RF daughter board with separate matching circuits for the single ended PA and differential LNA.

特性

  • RF frequency bands: 431MHz to 435MHz and 862MHz to 928MHz
  • Data rates supported: 9.6kbps, 38.4kbps, 50kbps, 100kbps, 200kbps,and 300kbps
  • Integrated packet management support
    • Insertion/detection of preamble/sync word/cyclic redundancy check(CRC)
    • Manchester and 8-bit/10-bit data encoding and decoding
    • Data whitening
  • 240-byte packet buffer for Tx/Rx data
  • Smart wake mode (SWM)
    • Autonomous carrier sense, packet sniffing, and reception
  • Integrated battery alarm and temperature sensor
  • Integrated RC oscillator
  • On-chip, 8-bit analog-to-digital converter (ADC)
  • 5mm × 5mm, 32-lead LFCSP package
  • Receiver performance
    • Highly linear:−11.5dBm input IP3
    • Blocking:76dB at 10MHz offset
    • Receiver sensitivity, bit error rate (BER)
      • 111dBm at 9.6kbps
      • 105dBm at 100kbps
    • Low power: 12.8mA in Rx

  • Modulation:two-level frequency (FSK) and Gaussian frequency (GFSK) shift keying
  • 2.2V to 3.6V power supply
  • Automatic frequency control (AFC) and automatic gain control (AGC)
  • Digital received signal strength indication (RSSI)
  • Fully integrated low noise RF synthesizer and transmit (Tx)/receive (Rx) switch
  • Image rejection calibration (patent pending)
  • Ultralow power sleep modes for long battery life
  • Simple serial port interface (SPI) control interface
  • Fast radio state transitions
  • Transmitter performance
    • High efficiency power amplifier (PA): 23.3mA in Tx at 10dBm
    • Output power range:−20dBm to +13.5dBm
    • Output power resolution:0.5dB
  • Low power mode performance
    • 0.33μA in PHY_SLEEP mode (Deep Sleep Mode 1)
    • 0.75μA in PHY_SLEEP mode (32kHz RC oscillator active)
    • 11.75μA autonomous Rx sniff using SWM, 300kbps
  • Supported regulations
    • ETSI EN 300 220
    • FCC Part 15.231, Part 15.247, Part 15.249

Functional Block Diagram

框图 - Analog Devices Inc. 亚德诺半导体  ADF7024 低功耗、次 GHz、收发器集成电路