Analog Devices Inc. HMC7043 时钟缓冲器
Analog Devices HMC7043 高性能时钟缓冲器管理在高速数据转换器中通过并联或串联(JESD204B) 接口配置的超低相位噪声基准的分配。 设计用于多载波 GSM 和 LTE 基站，该 3.2GHz HMC7043 时钟缓冲器具有多种分配和时钟管理特性。 这些特性可简化基带和无线电卡时钟树的设计。 得益于 14 路低噪声且可配置的输出，HMC7043 时钟缓冲器可以灵活地与基站收发台 (BTS) 系统中的 FPGA 和 ADC/DAC 组件接口。 这 14 个通道分别进行独立灵活的相位管理。 射频 SYNC 特性支持确定性同步多个 HMC7043 时钟缓冲器。 这种工作方式可简化组件之间的帧同步，同时确保所有时钟输出从同一时钟沿开始。 SPI 可编程功率/性能调整可确保对数据转换器的适当设置和维持时间。 HMC7043 器件在 2457.6MHz 条件下可实现小于 15fs rms 的抖动性能，从而提高了高速数据转换器的信噪比和动态范围。 该器件还具有 -155.2 dBc/Hz 的极低噪底 (983.04 MHz)，以分配小数 N LO 信号，同时具有出色的杂散性能。
With 14 low-noise and configurable outputs, the HMC7043 clock buffers provide flexibility in interfacing the FPGA and ADC/DAC components in base transceiver station (BTS) systems. Each of the 14 channels features independent, flexible phase management. The RF SYNC feature deterministically synchronizes multiple HMC7043 clock buffers. This operation simplifies frame alignment between the components and ensures that all clock outputs start with the same edge. SPI-programmable power/performance adjustment ensures proper setup and holds times for the data converters.
The HMC7043 devices achieve <15fs rms jitter performance at 2457.6MHz to improve a high-speed data converter’s signal-to-noise ratio and dynamic range. The devices also have a very low noise floor of −155.2dBc/Hz at 983MHz to distribute frac-N LO signals with excellent spurious performance.
特性
- JEDEC JESD204B support
- Low additive jitter: <15fs rms at 2457.6MHz (12kHz to 20MHz)
- Very low noise floor: −155.2dBc/Hz at 983.04MHz
- Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
- Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200MHz
- JESD204B-compatible system reference (SYSREF) pulses
- 25ps analog and ½ clock input cycle digital delay
- Independently programmable on each of 14 clock output channels
- SPI-programmable adjustable noise floor vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization - Supports deterministic synchronization of multiple HMC7043 devices
- RFSYNCIN pin or SPI-controlled SYNC trigger for output synchronization of JESD204B
- GPIO alarm/status indicator to determine system health
- Clock input to support up to 6GHz
- 48-lead, 7mm × 7mm LFCSP package
应用
- JESD204B clock generation
- Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
- Data converter clocking
- Phase array reference distribution
- Microwave baseband cards
Block Diagram
