特性
- Enhanced Mid-range Core with 49 Instruction, 16 Stack Levels
- Flash Program Memory with self-read/write capability
- eXtreme Low Power (XLP)
- IDLE and DOZE low power modes
- Peripheral Module Disable (PMD)
- Peripheral Pin Select (PPS)
- 4x 10-bit PWMs
- 2x Capture, Compare, PWM (CCP)
- Complementary Waveform Generator (CWG)
- Numerically Controlled Oscillator (NCO)
- 4x Configurable Logic Controller (CLC)
- 24 Channel 10-bit ADC with Voltage Reference
- 5-bit Digital to Analog Converter (DAC)
- 2x Comparators
- 1x 8-bit Timers (TMR0/TMR2)
- 2x 16-bit Timer (TMR1)
- Window Watchdog Timer (WWDT)
- Enhanced Power-On/Off-Reset
- Low-Power Brown-Out Reset (LPBOR)
- Programmable Brown-out Reset (BOR)
- In-Circuit Serial Programming (ICSP)
规范
- Program Memory Type Flash
- Program Memory 7KB
- CPU Speed 8MIPS
- RAM Bytes 512
- Digital Communication Peripherals
- 2-UART
- 2-SPI
- 2-I2C
- Capture/Compare/PWM Peripherals 2 CCP
- Timers:
- 1x 8-bit
- 2x 16-bit
- ADC: 24 channel, 10-bit
- Comparators 2
- Temperature Range -40ºC to +125ºC
- Operating Voltage Range 2.3V to 5.5V
- Package options
- 28-pin SPDIP
- 28-pin SOIC
- 28-pin SSOP
- 28-pin UQFN 4mm x 4mm
Block Diagram
Core Data Path Diagram
发布日期: 2016-11-23
| 更新日期: 2025-06-13

