Alliance Memory AS4C512M16D4D/1G8D4D 8Gb DDR4 SDRAMs
Alliance Memory AS4C512M16D4D/1G8D4D 8Gb DDR4 SDRAMs are high-speed dynamic random-access memory internally organized with eight banks or sixteen banks. These SDRAMs use an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface that transfers two data words per clock cycle at the I/O pins. The DDR4 SDRAMs offer a data bus write Cyclic Redundancy Check (CRC), read preamble training, control gear-down mode, per-DRAM Addressability (PDA), output driver impedance control, and ODT. The AS4C512M16D4D/1G8D4D 8Gb DDR4 SDRAMs comply with JEDEC standard and RoHS. Typical applications include industrial, medical, networking, IoT, automotive, gaming, 5G designs, enterprise, and computing and server applications.
Features
- JEDEC standard compliant
- Up to 1600MHz fast clock rate
- Power supplies:
- VDD and VDDQ = +1.2V ±0.06V
- VPP = +2.5V -0.125V/+0.25V
- Operating temperature:
- TC = 0°C to 95°C commercial (extended)
- TC = -40°C to 95°C industrial
- Supports JEDEC clock jitter specification
- Bidirectional differential data strobe, DQS &DQS#
- Differential clock, CK, and CK#
- 8 internal banks with 2 groups of 4 banks each (AS4C512M16D4D)
- 16 internal banks with 4 groups of 4 banks each (AS4C1G8D4D)
- Separated IO gating structures by bank group
- 8n-bit prefetch architecture
- Precharge and active power down
- Auto refresh and self refresh
- Low-Power Auto Self Refresh (LPASR)
- Self refresh abort
- Fine granularity refresh
- Dynamic ODT (RTT_PARK and RTT_Nom and RTT_WR)
- Write leveling
- DQ training via MPR
- Programmable preamble is supported both of 1tCK and 2tCK mode
- Command/Address (CA) parity
- Data bus write Cyclic Redundancy Check (CRC)
- Boundary scan mode (AS4C512M16D4D)
- Internal VREFDQ training
- Read preamble training
- Control gear down mode
- Per DRAM Addressability (PDA)
- Output driver impedance control
- Dynamic On-Die Termination (ODT)
- Input Data Mask (DM) and Data Bus Inversion (DBI)
- ZQ calibration
- Command/Address Latency (CAL)
- Maximum Power Saving Mode (MPSM) (AS4C1G8D4D)
- Asynchronous reset
- DLL enable/disable
- Burst length (BL8/BC4/BC4 or 8 on the fly)
- Sequential/interleave burst type
- CAS Latency (CL)
- CAS Write Latency (CWL)
- 0, CL-1, and CL-2 Additive Latency (AL)
- Average refresh period:
- 8192 cycles/64ms (7.8us at -40°C ≤ TC ≤ +85°C)
- 8192 cycles/32ms (3.9us at +85°C < TC ≤ +95°C)
- Pseudo Open Drain (POD) data interface
- RoHS compliant
- Hard Post Package Repair (hPPR)
- Soft Post Package Repair (sPPR)
- Pb-free and halogen-free
- Package:
- 96-ball 7.5mm x 13mm x 1.2mm FBGA (AS4C512M16D4D)
- 78-ball 7.5mm x 10.5mm x 1.2mm FBGA (AS4C1G8D4D)
Applications
- Industrial
- Medical
- Networking
- Internet of Things (IoTs)
- Automotive
- Gaming
- 5G Designs
- Computers and servers
- Enterprise
Functional Block Diagram
