Analog Devices Inc. AD4880 Analog Front End
Analog Devices AD4880 Analog Front End (AFE) is a dual-channel, 20-bit successive approximation register (SAR) analog-to-digital converter (ADC) that integrates fully-differential drivers (FDA), gain-setting resistors, low-drift reference buffers, LDO regulators, and critical decoupling capacitors to simplify precision signal-chain design. The two channels can sample simultaneously or independently, giving designers flexibility across low-latency and multiplexed acquisition systems.
Optimized for input signals up to 1MHz, the AD4880 delivers low noise, high linearity, and low power while easing analog-front-end design and PCB layout constraints. The AD4880 AFE also supports oversampling with integrated digital filtering and decimation, two independent multilane LVDS interfaces for low-latency data transfer, and on-chip FIFO memory for asynchronous SPI data access when reducing host loading is a priority.
The ADI AD4880 is ideal for digital imaging, cell analysis, spectroscopy, high-speed data acquisition, digital control loops, power quality analysis, source measurement units, and nondestructive test systems. The device is offered in a 196-ball, 10mm x 10mm CSP_BGA package with 0.65mm pitch and supports an operating temperature range from -40°C to +85°C.
Features
- Integrated fully differential ADC drivers
- Wide input common-mode voltage range
- High common-mode rejection
- Integrated gain-setting resistors
- High performance
- 20-bit resolution with no missing codes
- 40MSPS throughput per channel
- 46.25ns conversion latency
- INL ±7.5ppm typical, ±12ppm maximum
- SNR/THD 92.6dBFS typical/-107.6dBc typical at fIN=1kHz
- SNR/THD 91.2dBFS typical/-108.0dBc typical at fIN=500kHz
- Noise spectral density -160.9dBFS/Hz
- Single-ended to differential conversion
- Gain options include 1.03, 1.25, 1.53, 2.03, 2.74, 4.11, and 5.77
- Low power at 120.5mW per channel, typical at 40MSPS
- Integrated low-drift reference buffers and decoupling
- Integrated VCM generation
- Digital features and data interface
- Conversion result FIFO with 16K samples per channel
- Digital averaging filter with up to 210 decimation
- SPI configuration per channel
- Configurable data interface per channel
- Single-lane DDR serial LVDS at 800Mbps per lane
- Dual-lane DDR serial LVDS at 400Mbps per lane
- Single/quad lane SPI data interface
Applications
- Digital imaging
- Cell analysis
- Spectroscopy
- High-speed data acquisition
- Digital control loops and hardware in the loop
- Power quality analysis
- Source measurement units
- Nondestructive test
Specifications
- Dual-channel SAR ADC with simultaneous or independent sampling
- Optimized for input signals up to 1MHz
- Differential input voltage range depends on the selected gain path and input pins
- FDA input common-mode voltage supports ±2.91V functional range at SJ pins
- VREFIN input 3.0V nominal with integrated reference buffering
- LVDS outputs follow EIA-644 signaling with selectable differential output levels
- Supply domains include ±VS, VDD33, VDDLDO, VDD11ChX, and IOVDDChX
- ±VS Supply range 3V to 10V with typical operation at +5V and -1V
- Package
- 196-ball CSP_BGA
- 10mm x 10mm body, 0.65mm pitch
- Operating temperature range of -40°C to +85°C
Additional Resource
FUNCTIONAL BLOCK DIAGRAM
