Analog Devices Inc. AD9250 双通道14位模数转换器
Analog Devices AD9250 双通道14位模数转换器(ADC)，最高采样速率250MSPS，旨在为低成本、小尺寸、宽带宽、多功能通信应用领域提供支持。可配置JESD204B输出接口每个通道的最高速率能够达到5Gbps。ADC内核采用多级、差分廉线结构，并集成了输出纠错逻辑。ADC内核具有宽带宽输入，支持用户可选的各种输入范围。集成基准电压源可简化设计。占空比稳定器可用来补偿ADC时钟占空比的波动，使转换器保持出色的性能。JESD204B高速串行接口可降低电路板布线要求，并减少接收器件所需的引脚数量。
The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
特性
- JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
- Signal-to-noise ratio (SNR) = 70.6dBFS at 185MHz AIN and 250MSPS
- Spurious-free dynamic range (SFDR) = 88dBc at 185MHz AIN and 250MSPS
- 711mW at 250 MSPS Total power consumption
- 1.8V supply voltages
- Integer 1-to-8 input clock divider
- Sample rates of up to 250MSPS
- IF sampling frequencies of up to 400MHz
- Internal analog-to-digital converter (ADC) voltage reference
应用
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- I/Q demodulation systems
- Smart antenna systems
- Electronic test and measurement equipment
- RADAR receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
Block Diagram
发布日期: 2013-04-18
| 更新日期: 2022-03-11