Analog Devices Inc. AD9554 时钟转换器
Analog Devices AD9554 是一款低环路带宽时钟转换器，可针对包括同步光纤网络(SONET/SDH)的许多系统提供抖动清除和同步功能。AD9554 产生的输出时钟可以与多达四路的外部输入参考时钟同步。AD9554 的消耗功率仅为 940mW，但可以产生 430kHz 到 941MHz 输出范围的八个输出时钟，这些时钟可同步到四个 2kHz 到 1GHz 的外部输入基准，而回路带宽可低至 0.1Hz。AD9554 时钟的高集成度、自适应时钟功能及 DPLL 内置的 OTN 映射算法可降低系统成本，方法是通过简化时钟电路并避免软件控制例程。输出抖动在 50kHz 到 80MHz 的范围内是 250fs，在 12kHz 到 20MHz 的范围内是 350fs。四个模数锁相环(PLL)可以降低与外部基准时钟相关的输入时间抖动或相位噪声。借助数字控制环路和保持电路，即使所有基准时钟都已失效，AD9554 也可以连续产生低抖动的输出时钟。AD9554 工作于 -40°C 到 +85℃ 的工业温度范围，适用于网络同步、基准时钟抖动清除、含 FEC 的最高达到 OC-192 的 SONET/SDH 时钟、Stratum 3 保持、抖动清除及相位瞬态控制、线缆基础设施、数据通信等应用领域。
The AD9554 clock's high level of integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250fs over the 50kHz to 80MHz range and 350fs over the 12kHz to 20MHz range. The four analog-digital phase-locked loops (ADPLL) allow for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. AD9554 operates over an industrial temperature range of −40°C to +85°C and is ideal for network synchronization, cleanup of reference clock jitter, SONET/SDH clocks up to OC-192, including FEC, Stratum 3 holdover, jitter cleanup, and phase transient control, cable infrastructure, and data communications.
特性
- Supports GR-1244 Stratum 3 stability in holdover mode
- Supports smooth reference switchover with virtually no disturbance on output phase
- Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
- Supports ITU-T G.8262 synchronous Ethernet slave clocks
- Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261
- Auto/manual holdover and reference switchover
- Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
- Quad analog digital phase-locked loop (DPLL) architecture with
- Four reference inputs (single-ended or differential)
- Eight outputs (single-ended or differential)
- 4 × 4 crosspoint allows any reference input to drive any PLL
- Input reference frequencies from 2kHz to 1000MHz
- Reference validation and frequency monitoring: 2ppm
- Programmable input reference switchover priority
- 20-bit programmable input reference divider
- 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECL-compatible
- 430kHz to 941MHz Output frequency range
- Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL
- Programmable loop bandwidths from 0.1Hz to 4kHz
- Loop bandwidth as low as 0.1Hz to guarantee SyncE compliance
- Optional off-chip EEPROM to store power-up profile
- 72-lead (10mm × 10mm) LFCSP package
应用
- Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping
- Cleanup of reference clock jitter
- SONET/SDH clocks up to OC-192, including FEC
- Stratum 3 holdover, jitter cleanup, and phase transient control
- Cable infrastructure
- Data communications
Block Diagram
