Analog Devices Inc. AD9652 16 位模数转换器（ADC）
Analog Devices AD9652 16 位模数转换器（ADC）是一款采样速率最高达 310MSPS 的双通道 ADC。它被设计用于对需要在宽幅输入频率范围（高达 465MHz）上有优异动态范围的高要求、高速信号处理应用提供支持。其优异的、-157.6dBFS 低噪声本底和较高的信号无杂散动态范围（SFDR）性能（典型值超过 85dBFS）可在大信号存在的情况下分辨出低电平信号。其双 ADC 内核采用多级、流水线架构，并集成了输出纠错逻辑。高性能片上缓冲器和内部电压基准使接口对外部驱动电路简化，同时保持模数转换器的优异性能。
特性
- High dynamic range
- SNR = 75.0dBFS at 70MHz (AIN = −1dBFS)
- SFDR = 87dBc at 70MHz (AIN = −1dBFS)
- Noise spectral density (NSD) = −156.7dBFS/Hz input noise at −1dBFS at 70MHz
- NSD = −157.6dBFS/Hz for small signal at −7dBFS at 70MHz
- 90dB channel isolation/crosstalk
- On-chip dithering (improves small signal linearity)
- Excellent IF sampling performance
- SNR = 73.7dBFS at 170MHz (AIN = −1dBFS)
- SFDR = 85dBc at 170MHz (AIN = −1dBFS)
- Full power bandwidth of 465MHz
- On-chip 3.3V buffer
- Programmable input span of 2V p-p to 2.5V p-p (default)
- Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24GHz)
- Internal ADC clock duty cycle stabilizer
- SYNC input allows multichip synchronization
- Total power consumption: 2.16W
- 3.3V and 1.8V supply voltages
- DDR LVDS (ANSI-644 levels) outputs
- Serial port control
- Energy saving power-down modes
应用
- Military radar and communications
- Multimode digital receivers (3G or 4G)
- Test and instrumentation
- Smart antenna systems
Functional Block Diagram
发布日期: 2014-07-10
| 更新日期: 2022-03-11