The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The core also features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Flexible power-down options allow significant power savings, when desired.
特性
- JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
- Signal-to-noise ratio (SNR) = 70.6dBFS at 185MHz AIN and 250MSPS
- Spurious-free dynamic range (SFDR) = 88dBc at 185MHz AIN and 250MSPS
- 434mW at 250MSPS Total power consumption
- 1.8V supply voltages
- Integer 1-to-8 input clock divider
- Sample rates of up to 250MSPS
- IF sampling frequencies of up to 400MHz
- Internal analog-to-digital converter (ADC) voltage reference
- Flexible analog input range
- 1.4V p-p to 2.0V p-p (1.75V p-p nominal)
- ADC clock duty cycle stabilizer (DCS)
- Serial port control
- Energy saving power-down modes
应用
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- Smart antenna systems
- Electronic test and measurement equipment
- Radar receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
Block Diagram
Associated Eval Board
发布日期: 2013-05-31
| 更新日期: 2022-03-11

