Infineon Technologies PSoC®4100M ARM 微控制器

Cypress Semiconductors PSoC®4100M ARM 微控制器是一系列带有 ARM® Cortex™-M0 CPU 的可编程嵌入式系统控制器。 该微控制器将可编程和可配置模拟和数字块与灵活的自动路由相结合。 PSoC4100M ARM 微控制器具有 24MHz ARM Cortex-M0 CPU,带单周期乘法和高达 128kb 的闪存和读取加速器。 这些微控制器是兼容 PSoC 4 平台的构件,可以满足新的应用和设计需要。 PSoC4100M 具有可编程模拟和数字子系统,可对设计进行灵活的现场调试。

特性

  • 32-bit MCU subsystem
    • 24MHz Arm Cortex-M0 CPU with single-cycle multiply
    • Up to 128kB of flash with Read Accelerator
    • Up to 16kB of SRAM
    • DMA engine
  • Programmable analog
    • Four opamps that operate in Deep Sleep mode at very low current levels
    • All opamps have reconfigurable high current pin-drive, high-bandwidth internal drive, ADC input buffering, and comparator modes with flexible connectivity allowing input connections to any pin
    • Four current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
    • Two low-power comparators that operate in Deep Sleep mode
    • 12-bit SAR ADC with 806Ksps conversion rate
  • Low power 1.71V to 5.5V operation
    • 20nA stop mode with GPIO pin wakeup
    • Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs
  • Capacitive sensing
    • Cypress Capacitive Sigma-Delta (CSD) technique provides best-in-class SNR (>5:1) and water tolerance
    • Cypress-supplied software component makes capacitive sensing design easy
    • Automatic hardware tuning (SmartSense™)
  • Segment LCD drive
    • LCD drive supported on all pins (common or segment)
    • Operates in Deep Sleep mode with 4 bits per pin memory
  • Serial communication
    • Four independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality
  • Timing and pulse-width modulation
    • Eight 16-bit timer/counter pulse-width modulator (TCPWM) blocks
    • Center-aligned, Edge, and Pseudo-random modes
    • Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
  • Package options
    • 68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin TQFP packages
    • Up to 55 programmable GPIOs
    • GPIO pins can be CapSense, LCD, analog, or digital
    • Drive modes, strengths, and slew rates are programmable
  • PSOC Creator Design Environment
    • Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
    • Applications Programming Interface (API component) for all fixed-function and programmable peripherals
  • Industry-standard tool compatibility
    • After schematic entry, development can be done with Arm-based industry-standard development tools

Block Diagram

框图 - Infineon Technologies PSoC®4100M ARM 微控制器
发布日期: 2016-04-21 | 更新日期: 2025-08-19