Kingston LPDDR4x Low-Power DRAMs

Kingston LPDDR4x Low-Power DRAMs support data rates up to 4266 Mb/s and maintain backward compatibility with lower speeds such as 3733, 3200, and 2666. These devices offer 16Gb and 32Gb device densities with double-data-rate architecture. The LPDDR4x DRAMs feature per-bank refresh, Partial Array Self-Refresh (PASR), and Auto Temperature Compensated Self-Refresh (ATCSR) power-saving options. These devices include eight internal banks per channel for concurrent operation, Burst Lengths (BL), programmable Read Latency (RL), and Write Latency (WL). The LPDDR4x DRAMs operate with multiple low‑voltages and are available in a 200-ball FBGA package.

Features

Low-power consumption
Per-bank refresh
Partial Array Self-Refresh (PASR):
- Bank masking
- Segment masking
Auto Temperature Compensated Self-Refresh(ATCSR) by built-in temperature sensor
All-bank auto refresh and directed per-bank auto refresh supported

Double-data-rate architecture; two data transfers per one clock cycle
Differential clock inputs (CK_t and CK_c)
Bi-directional differential data strobe(DQS_tandDQS_c)
Commands entered on both rising and falling CK_t edge, data and data mask referenced to both edges of DQS_t
DMI pin support for write data masking and DBIdc functionality

Specifications

Device density:
- 16Gb (512M x 16 I/O x 2 channels)
- 32Gb (1024M x 16 I/O x 2 channels)
16Gb die density
Organization:
- x 32 bits: 64M words x 32 bits x 8 banks
- 2 pieces of 16Gb (x32) in one package(For 32Gb case)
- R0 to R15 row address
- C0 to C9 column address
Power supply:
- VDD1 = 1.80V (1.70V to 1.95V)
- VDD2 = 1.10V (1.06V to 1.17V)
- VDDQ = 0.60V (0.57V to 0.65V)

Data rate:
- 4266Mbps maximum
- 3733, 3200, 2666, 2400, and lower speed backward compatible
Eight internal banks per channel for concurrent operation
Burst lengths (BL)- 16, 32, and on-the-fly mode
Programmable Read Latency (RL) and Write Latency (WL)
Auto precharge option for each burst access
Programmable driver strength
Auto-refresh and self-refresh
8192 cycles/32ms refresh cycles (3.9μs average refresh period)
64-bit burst starting address boundary