STMicroelectronics STNRGxxxA 数字控制器

意法半导体 STNRGxxxA 数字控制器属于 STNRG 数字装置系列,用于先进的功率转换应用。STNRG 系列改进了成功的 STLUX™ 系列的设计,构成了众多 LED 驱动器构造的一部分。支持工业功率转换应用,如用于智能电源的 PFC+LLC、交错 LC DC/DC、交错 PFC,以及用于电动汽车试验线路驱动器的全电桥。

特性

  • Up to 6 programmable PWM generators (SMED - "State Machine Event Driven")
    • 10ns event detection and reaction
    • 1.3ns maximum PWM resolution
    • Single, coupled and two coupled operational modes
    • Up to 3 internal/external events per SMED
  • 4 analog comparators
    • 4 internal 4-bit references
    • Up to 4 external references
    • Less than 50ns propagation time
    • Continuous comparison cycle
    • Configurable hysteresis voltage levels
  • ADCs (up to 8 channels)
    • 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent
    • Sequencer functionality
    • 1M input impedance
    • x1 and x4 configurable gain value
  • Memories
    • Flash and E2PROM with read while write (RWW) and error correction code (ECC)
    • 32Kbytes Flash program memory; data retention 15 years at +85°C after 10 kcycles at +25°C
    • 1Kbyte data memory true data E2PROM; data retention: 15 years at 85°C after 100 kcycles at +85°C
    • 6Kbytes RAM
  • -40°C to +105°C operating temperature range
  • Integrated microcontroller
    • Advanced STM8® core with Harvard architecture and 3-stage pipeline
    • 16MHz maximum fCPU
  • Clock management
    • Internal 96MHz PLL
    • Low power oscillator circuit for external crystal resonator or direct clock input
    • Internal, user-trimmable 16MHz RC and low power 153.6kHz RC oscillators
    • Clock security system with clock monitor
  • Basic peripherals
    • System, auxiliary and basic timers
    • IWDG/WWDG watchdog, AWU, ITC
  • Reset and supply management
    • Multiple low power modes (wait, slow, auto-wakeup, Halt) with user definable clock gating
    • Low consumption power-on and power-down reset
  • I/O
    • Multifunction bidirectional GPIO with highly robust design, immune against current injection
    • Fast digital input DIGIN, with configurable pull-up
  • Communication interfaces
    • UART asynchronous with SW flow control and bootloader support
    • I2C master/slave fast-slow speed rate

System Architecture

应用电路图 - STMicroelectronics STNRGxxxA 数字控制器
发布日期: 2015-06-09 | 更新日期: 2022-03-11