Terasic Technologies TR10a-LP QDR™II+ Arria 10 FPGA Development Kit

Terasic Technologies TR10a-LP QDR™II+ Arria® 10 FPGA Development Kit offers an ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. The TR10a-LP delivers five independent banks of QDR™II+ SRAM and high-speed parallel flash memory for designs that demand high capacity and high speed for memory and storage.

The board is empowered with the Altera Arria 10 GX for system-level integration and flexibility. The Arria 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5Gbps, allowing the TR10a-LPQ to comply with version 3.0 of the PCI Express (PCIe) standard. The Arria 10 GX FPGA also allows ultra-low latency and straight connections to two external 40G QSFP+ modules.

Terasic Technologies TR10a-LP QDR™II+ Arria® 10 FPGA Development Kit is designed for demanding high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.

Features

  • Altera Arria® 10 GX FPGA (10AX115N2F45E1SG)
  • FPGA configuration
    • Onboard USB Blaster II for FPGA programming
    • Fast passive parallel (FPPx16) configuration via MAX II CPLD and flash memory
  • General user input/output
    • 4 LEDs
    • 2 push buttons
    • 2 dip switches
  • Clock system
    • 50MHz oscillator
    • Programmable clock generators Si5340A and Si53306
  • Mechanical specification: PCIe low-profile x16
  • Memory
    • QDR™II+ SRAM
    • Flash
  • Communication ports
    • 2 QSFP+ connectors
    • Dual PCIe x8 edge connector
    • 2x5 GPIO timing expansion header
  • System monitor and control
    • Temperature sensor
    • Fan control
    • Power monitor
    • UART to USB for board management
  • Power
    • PCIe 4-pin power connector, 12VDC input
    • PCIe edge connector power

Applications

  • High-frequency trading
  • High-performance computing
  • Data centers
  • Miltary and aerospace
  • 5G connectivity

Block Diagram

Block Diagram - Terasic Technologies TR10a-LP QDR™II+ Arria 10 FPGA Development Kit

Board Overview

Infographic - Terasic Technologies TR10a-LP QDR™II+ Arria 10 FPGA Development Kit
发布日期: 2019-05-07 | 更新日期: 2024-02-23