特性
- Five 3.3V Differential LVPECL Outputs
- Additive Jitter: 43fs RMS (typ) @ 312.5MHz
- Noise Floor (≥1 MHz offset):
- -158dBc/Hz (typ) @ 312.5MHz
- Output Frequency: 650MHz (max)
- Output Skew: 35ps (max)
- Part-to-Part Skew: 100ps (max)
- Propagation Delay: 0.37ns (max)
- Two Differential Input Pairs (pin-selectable)
- CLKx, nCLK Input Pairs can accept LVPECL,
- LVDS, HCSL, SSTL, LVHSTL, or Single-Ended Signals
- Synchronous Clock Enable
- Power Supply: 3.3V ±5%
- Package: 20-Lead TSSOP
- Industrial Temperature Range: -40°C to +85°C
应用
- Wireless and wired infrastructure
- Networking and data communications
- Servers and computing
- Medical imaging
- Portable test and measurement
- High end A/V
Block Diagram
发布日期: 2014-01-08
| 更新日期: 2022-03-11

