特性
- Quad channel
- 12-Bit Resolution
- Single 1.8V supply
- Flexible input clock buffer with divide-by-1, -2, -4
- SNR = 69.6dBFS, SFDR = 86dBc at fIN = 70MHz
- Ultra-low power consumption of 203mW/Ch at 160MSPS
- 105dB Channel isolation
- Internal dither
- JESD204B Serial interface:
- Subclass 0, 1, 2 compliant up to 3.2Gbps
- Supports one lane per ADC up to 160MSPS
- Support for multi-chip synchronization
- Pin-to-pin compatible with 14-Bit version
- VQFN-48 (7mm × 7mm) Package
应用
- Multi-carrier, multi-mode cellular base stations
- Radar and smart antenna arrays
- Munitions guidance
- Motor control feedback
- Network and vector analyzers
- Communications test equipment
- Nondestructive testing
- Microwave receivers
- Software Defined Radios (SDRs)
- Quadrature and diversity radio receivers
Functional Block Diagram
发布日期: 2015-04-20
| 更新日期: 2025-06-25

