特性
- Fully Differential Amplifier (FDA) Architecture
- 500 MHz (G = 2V/V) Bandwidth
- 850MHz Gain Bandwidth Product
- 1500V/µs Slew Rate
- HD2: -95dBc at 10MHz (2VPP, RL = 500Ω)
- HD3: -90dBc at 10MHz (2VPP, RL = 500Ω)
- Input Voltage Noise: 2.2nV/Hz (f > 100kHz)
- Low offset drift: ±0.5µV/°C (typ)
- Negative Rail Input (NRI)
- Rail-to-Rail Output (RRO)
- Robust Operation for Rload ≥ 50Ω
- Output Common-Mode Control
- Power Supply
- Single-Supply Voltage Range: 2.7V to 5.4V
- Split-Supply Voltage Range: ±1.35V to ±2.7V
- Quiescent Current: 10.1mA (5V Supply)
- Power-Down Capability: 2µA (typ)
应用
- Low-Power, High-Performance ADC Driver
- SAR, ΔΣ, and Pipeline
- Low Power, High Performance (DC or AC Coupled)
- Single-Ended to Differential Amplifier
- Differential to Differential Amplifier
- Differential Active Filters
- Differential Transimpedance for DAC Outputs
- DC- or AC-Coupled Interface to the ADC3xxx Family of Low-Power, High-Performance ADCs
- Pin-Compatible Upgrade to ADA4932-1 (RGT)
Datasheets
Functional Block Diagram
发布日期: 2014-09-18
| 更新日期: 2024-08-09

