SATA3 Host CPUless IP Core

Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system containing the application, transport, and link layers in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed using an HDL code to control the transceiver following the SATA protocol. The interface module is connected between the SATA3H-CL IP and the SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features a dgIF typeS user interface that is very easy to access and comes with a control and data interface.

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Design Gateway 开发软件 CPU less SATA Host IP core for Intel Arria 10 SX
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数据表
IP Core - SATA3H-CL Intel Arria 10 SX
Design Gateway 开发软件 CPU less SATA Host IP core for Intel Arria V ST
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数据表
IP Core - SATA3H-CL Intel Arria V ST
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Artix-7
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数据表
IP Core - SATA3H-CL Xilinx Artix-7
Design Gateway 开发软件 CPU less SATA Host IP core for Intel Cyclone 10 GX
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数据表
IP Core - SATA3H-CL Intel Cyclone 10 GX
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Kintex-7
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数据表
IP Core - SATA3H-CL Xilinx Kintex-7
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Kintex UltraScale
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数据表
IP Core - SATA3H-CL Xilinx Kintex UltraScale
Design Gateway 开发软件 CPU less SATA Host IP core for Intel Stratix V GX
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数据表
IP Core - SATA3H-CL Intel Stratix V GX
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Virtex-7
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数据表
IP Core - SATA3H-CL Xilinx Virtex-7
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Virtex UltraScale+
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数据表
IP Core - SATA3H-CL Xilinx Virtex UltraScale+
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Zynq-7000
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数据表
IP Core - SATA3H-CL Xilinx Zynq-7000
Design Gateway 开发软件 CPU less SATA Host IP core for Xilinx Zynq UltraScale+
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数据表
IP Core - SATA3H-CL Xilinx Zynq UltraScale+