MaxLinear MxL1600 Integrated Quad RF Transceiver
MaxLinear MxL1600 Integrated Quad RF Transceiver is a family of highly integrated and low-power consumption multi-port radio frequency (RF) transceivers for wireless infrastructure radios. The device's powerful combination of high integration, ultra-low power dissipation, high performance, and software-defined programmability makes it an optimal solution for 2G, 3G, 4G, and 5G macro, massive Multiple-Input/Multiple-Output (MIMO), and small cell radio platforms.
The MxL1600 family integrates four transmitters (Tx), four receivers (Rx), and up to two feedback receivers (FBRX). These devices are tunable to operate over a frequency range from 380MHz to 6000MHz. Each Rx is configurable to support wide signal bandwidths up to 400MHz. Each Tx and FBRX is configurable to support wider signal bandwidths up to 850MHz to facilitate digital pre-distortion algorithms.
The MxL1600 series delivers software-defined bandwidth and tuning flexibility with power efficiency via a direct-conversion RF architecture. This architecture is underpinned by integrated digital radio processing functions and low-noise, on-chip local oscillators (LO). An optional external Rx LO input is available when supporting Multi-RAT GSM.
The MaxLinear MxL1600 supports a JESD204 system interface, programmable to operate in either JESD204B or JESD204C mode with lane rates up to 32Gbps. It has an embedded microcontroller subsystem that simplifies configuration, calibration, and management of the device. The MxL1600 family is pin and software compatible with the MxL1500 series. Alternatively, users can choose the MxL1500 for radios that do not support multi-RAT GSM.
Features
- Four transmitters
- Four receivers
- Up to two feedback receivers
- Integrated dual-input RF switches per FBRX
- RF range from 380MHz to 6000MHz
- Rx bandwidth up to 400MHz
- Tx/FBRX synthesis bandwidth over 850MHz
- 2G/3G/4G/5G air interface support
- External LO input for multi-RAT GSM mode
- FDD and TDD operation
- Ultra-low power consumption
- Fast power-up and power-down modes
- Deep sleep power saving modes
- Tx power amplifier protection
- Rx gain control
- IQ Imbalance and LO feed-through correction
- JESD204B or JESD204C system interface
- Up to eight JESD204 TX lanes
- Up to eight JESD204 RX lanes
- Embedded CPU for control, calibration, and status reporting
- SPI control interface
- GPIO for fast control and status reporting
- JTAG boundary scan, including support for AC-coupled differential SERDES interfaces
- 1.8V, 1.2V, 0.8V, and 0.76V power supplies
- 15mm x 15mm, 324 balls, 0.8mm pitch FCBGA package with exposed die
- Supported Standards
- 3GPP Single RAT UTRA and E-UTRA
- 3GPP Multi-RAT GSM, UTRA, and E-UTRA
- 3GPP 5G NR Standard
- JEDEC JESD204B, Subclasses 0 and 1
- JEDEC JESD204C, Subclasses 0 and 1
- JTAG IEEE1149.1 and IEEE1149.6
Applications
- 2G/3G/4G/5G Macro-cell radios
- Massive MIMO radios
- Small cell radios
- Distributed Antenna Systems (DAS)
- Repeaters
Block Diagram
