Altera Arria® V 中端 FPGA

Altera Arria® V 中端 FPGA 包含最为全面的多款中端 FPGA 产品，其中既有适用于每秒6千兆位 (Gbps)和10千兆位应用的最低功耗型号，又有带宽最高且带有 12.5Gbps 收发器的型号。Arria® V 器件特别适用于功耗敏感型无线基础设施设备、20G/40G 桥接、交换、包处理应用、高清视频处理和图像处理以及密集型数字信号处理 (DSP)等应用场合。

特性

Two variants:
- Arria V GT FPGAs offer low-power mid-range FPGA for applications that require up to 20 transceivers at 10.3125Gbps and SFF 8431 compliance
- Arria V GX FPGAs offer low-power mid-range FPGA for applications that require up to 32 backplane-capable 6.5536Gbps transceivers
Low static power
Improved logic integration and differentiation capabilities
Increased bandwidth capacity
Hard-processor system (HPS) with integrated Arm® Cortex®-A9 MPCore processor
Internal memory blocks
- M10K-10Kb memory blocks with soft error correction code (ECC)
- M20K-20Kb memory blocks with hard ECC (Arria V GZ devices only)
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 50% of the ALMs as MLAB memory

Embedded hard IP blocks
Low system cost
TSMC's 28nm process technology
Thermal composite flip-chip BGA packaging
High-performance FPGA fabric
Clock networks
- Up to 650MHz global clock network
- Global, quadrant, and peripheral clock networks
- Clock networks that are not used can be powered down to reduce dynamic power
Phase-locked loops (PLLs)
FPGA general-purpose I/Os (GPIOs)
External memory interface
Memory interfaces with low latency (low-power high-speed serial interface)