特性
- Advanced programmable PLL design
- Very low jitter and phase noise (30ps to 70ps Pk-Pk typical)
- Up to 3 programmable outputs
- Output frequency up to 200MHz CMOS
- Accepts crystal or reference clock inputs:
- Fundamental crystal: 10MHz to 30MHz
- 3RD overtone crystal: Up to 75MHz
- Reference input: Up to 200MHz
- Accepts <1.0V reference signal input voltage
- Programmable I/O pin:
- Programmable clock
- Frequency selection input
- Output enable (OE)
- Power down (PDB) input
- Package types: 8-pin MSOP/SOP, 6-pin SOT
- Green/RoHS compliant
规范
- Product type: Low Power
- PLLs: 1
- Input frequency crystal: 10MHz to 30MHz
- Input frequency reference: 1MHz to 200MHz
- Number of outputs: ≤3
- Voltage: 2.5V, 3.3V
- PDB: True
- OE: True
- FSEL: True
- CSEL: False
- CLK: True
- Output logic: LVCMOS
- Function: Programmable, OE, FSEL, CLK2
- Ultra low power: False
- Output frequency range: 60MHz to 160MHz
- Operating temperature range: -40°C to +85°C
Block Diagram
发布日期: 2017-05-01
| 更新日期: 2022-03-11

